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| ASIC Design/Verification Engineer
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| ASIC Design/Verification Engineer
9 years in Asic front end. Proficient in VHDL, Vera, Verilog, SystemVerilog. Good knowledge of C/C++ and Perl.
Languages spoken: English, Hindi and Malayalam | |
| Resume reference: | mu7IKInG | |
| Date last updated: | October 5, 2008 | |
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| Education: | Post-graduate degree - M Tech in Electronics | |
| Experience: | 5-9 years | |
| Employment situation: | In permanent employment | |
| Salary expectations: | Negotiable | |
| Availability: | From January 3, 2009 | |
| Type of employment: | Full Time, Part Time | |
| Location: | Abroad - India | |
| Looking to work in: | AB/Calgary, AB/Edmonton, AB/Other, BC/Abbotsford, BC/Kelowna, BC/Vancouver, BC/Victoria, BC/Other, MB/Winnipeg, MB/Other, NB/Fredericton, NB/Moncton, NB/St.John, NB/Other, NF/St.John's, NT/Northwest Terr., NS/Halifax, NS/Other, NU/Nunavut, ON/Grt.Sudbury, ON/Hamilton, ON/Kingston, ON/Kitchener, ON/London, ON/Oshawa, ON/Ottawa, ON/St.Catharines, ON/Thunder Bay, ON/Toronto/GTA, ON/Windsor, ON/Other, PE/Prince Edward I., QC/Montréal, QC/Québec, SK/Regina | |
| Age: | | |
| Gender: | | |
| Marital status: | | |
| Own transport: | Yes | |
| Driver's license: | Yes | |
| Citizenship: | | |
| Right to work | No, I need sponsorship | |
| English level: | Fluent | |
| French level: | Basic | |
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