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| Electrical Engineer
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| • Extensive design & development experience on FPGA and CPLD platforms with Xilinx Spartan, Virtex-V pro and Altera Max-II families
• In depth knowledge of VLSI CAD and ASIC design tools including VHDL, Cadence, Synopsys, Xilinx ISE, XST and Matlab System Generator
• Design experience at RTL level for architectural synthesis of Application Specific Processor (ASP)
• Work experience in design and development of instrumentation and testing hardware
• Excellent knowledge of data structures in C and C++ with Graduate Assistance teaching experience
• Knowledge of computer networks, wireless technologies, 802.11 a, b, g protocols: CCNA associate
• Embedded system and Reconfigurable system design
• Simulation and modeling with Model Sim, MATLAB/SIMULINK, System Generator
• Research Assistant in optimization and algorithm design lab (OPRAL) at Ryerson University
• Excellent Communication, Organizational and Time Management skills
• Licensed as Engineer Intern Trainee (EIT) with Professional Engineers Ontario (PEO)
• Excellent academic record with 3.77/4 GPA
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| Resume reference: | suL3GSeT | |
| Date last updated: | November 5, 2009 | |
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| Education: | Post-graduate degree - MS VLSI & Digital Design | |
| Experience: | 1 year | |
| Employment situation: | In traineeship | |
| Salary expectations: | 50000 cad | |
| Availability: | From February 3, 2010 | |
| Type of employment: | Full Time, Part Time, Temporary, Traineeship | |
| Location: | ON/Toronto/GTA - Brampton | |
| Looking to work in: | Abroad, AB/Calgary, AB/Edmonton, AB/Other, BC/Vancouver, BC/Victoria, BC/Other, ON/Grt.Sudbury, ON/Hamilton, ON/Kingston, ON/Kitchener, ON/London, ON/Oshawa, ON/Ottawa, ON/St.Catharines, ON/Thunder Bay, ON/Toronto/GTA, ON/Windsor, ON/Other | |
| Age: | 24 | |
| Gender: | Male | |
| Marital status: | Single | |
| Own transport: | Yes | |
| Driver's license: | Yes | |
| Citizenship: | Permanent Resident | |
| Right to work | Yes, I have citizenship | |
| English level: | Native speaker | |
| French level: | Zero | |
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