• Extensive design & development experience on FPGA and CPLD platforms with Xilinx Spartan, Virtex-V pro and Altera Max-II families • In depth knowledge of VLSI CAD and ASIC design tools including VHDL, Cadence, Synopsys, Xilinx ISE, XST and Matlab System Generator • Design experience at RTL level for architectural synthesis of Application Specific Processor (ASP) • Work experience in design and development of instrumentation and testing hardware • Excellent knowledge of data structures in C and C++ with Graduate Assistance teaching experience • Knowledge of computer networks, wireless technologies, 802.11 a, b, g protocols: CCNA associate • Embedded system and Reconfigurable system design • Simulation and modeling with Model Sim, MATLAB/SIMULINK, System Generator • Research Assistant in optimization and algorithm design lab (OPRAL) at Ryerson University • Excellent Communication, Organizational and Time Management skills • Licensed as Engineer Intern Trainee (EIT) with Professional Engineers Ontario (PEO) • Excellent academic record with 3.77/4 GPA